Add instruction selection for arithmetic operations

This commit is contained in:
Laborratte 5 2025-05-17 17:19:17 +02:00
parent f7441e155a
commit bbacc928ae
Signed by: Laborratte5
GPG key ID: 3A30072E35202C02
2 changed files with 60 additions and 0 deletions

View file

@ -12,12 +12,17 @@ import edu.kit.kastel.vads.compiler.backend.aasm.AasmRegisterAllocator;
import edu.kit.kastel.vads.compiler.backend.regalloc.Register;
import edu.kit.kastel.vads.compiler.backend.regalloc.RegisterAllocator;
import edu.kit.kastel.vads.compiler.ir.IrGraph;
import edu.kit.kastel.vads.compiler.ir.node.AddNode;
import edu.kit.kastel.vads.compiler.ir.node.Block;
import edu.kit.kastel.vads.compiler.ir.node.ConstIntNode;
import edu.kit.kastel.vads.compiler.ir.node.DivNode;
import edu.kit.kastel.vads.compiler.ir.node.ModNode;
import edu.kit.kastel.vads.compiler.ir.node.MulNode;
import edu.kit.kastel.vads.compiler.ir.node.Node;
import edu.kit.kastel.vads.compiler.ir.node.ProjNode;
import edu.kit.kastel.vads.compiler.ir.node.ReturnNode;
import edu.kit.kastel.vads.compiler.ir.node.StartNode;
import edu.kit.kastel.vads.compiler.ir.node.SubNode;
public class X86CodeGenerator implements CodeGenerator {
@ -63,6 +68,11 @@ public class X86CodeGenerator implements CodeGenerator {
// TODO: implement code generation
switch (node) {
case AddNode add -> addNode(builder, registers, add);
case SubNode sub -> subNode(builder, registers, sub);
case MulNode mul -> mulNode(builder, registers, mul);
case DivNode div -> divNode(builder, registers, div);
case ModNode mod -> modNode(builder, registers, mod);
case ConstIntNode c -> constIntNode(builder, registers, c);
case ReturnNode r -> returnNode(builder, registers, r);
case Block _, ProjNode _, StartNode _ -> {
@ -95,4 +105,53 @@ public class X86CodeGenerator implements CodeGenerator {
.append(registers.get(c));
}
private static void addNode(StringBuilder builder, Map<Node, Register> registers, AddNode node) {
builder.repeat(" ", 2)
.append("add ")
.append(registers.get(predecessorSkipProj(node, AddNode.LEFT)))
.append(",")
.append(registers.get(predecessorSkipProj(node, AddNode.RIGHT)));
}
private static void subNode(StringBuilder builder, Map<Node, Register> registers, SubNode node) {
builder.repeat(" ", 2)
.append("sub ")
.append(registers.get(predecessorSkipProj(node, SubNode.LEFT)))
.append(",")
.append(registers.get(predecessorSkipProj(node, SubNode.RIGHT)));
}
private static void mulNode(StringBuilder builder, Map<Node, Register> registers, MulNode node) {
builder.repeat(" ", 2)
.append("imul ")
.append(registers.get(predecessorSkipProj(node, MulNode.LEFT)))
.append(",")
.append(registers.get(predecessorSkipProj(node, MulNode.RIGHT)));
}
private static void divNode(StringBuilder builder, Map<Node, Register> registers, DivNode node) {
builder.repeat(" ", 2)
.append("mov ")
.append(registers.get(predecessorSkipProj(node, DivNode.LEFT)))
.append(",")
.append(registers.get(node))
.append("\n");
builder.repeat(" ", 2)
.append("idiv ")
.append(registers.get(predecessorSkipProj(node, DivNode.RIGHT)));
}
private static void modNode(StringBuilder builder, Map<Node, Register> registers, ModNode node) {
builder.repeat(" ", 2)
.append("mov ")
.append(registers.get(predecessorSkipProj(node, ModNode.LEFT)))
.append(",")
.append(registers.get(node))
.append("\n");
builder.repeat(" ", 2)
.append("idiv ")
.append(registers.get(predecessorSkipProj(node, ModNode.RIGHT)));
}
}

View file

@ -13,4 +13,5 @@ _main:
mov $1,%0
mov $2,%1
add %0,%1
mov %0,%eax
ret