Add outline for x68 asm code generation

This commit is contained in:
Laborratte 5 2025-05-12 16:32:45 +02:00
parent 5988187c1d
commit 3cfe211bf6
Signed by: Laborratte5
GPG key ID: 3A30072E35202C02

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@ -0,0 +1,64 @@
package edu.kit.kastel.vads.compiler.backend.x86asm;
import java.util.HashSet;
import java.util.List;
import java.util.Map;
import java.util.Set;
import edu.kit.kastel.vads.compiler.backend.CodeGenerator;
import edu.kit.kastel.vads.compiler.backend.aasm.AasmRegisterAllocator;
import edu.kit.kastel.vads.compiler.backend.regalloc.Register;
import edu.kit.kastel.vads.compiler.backend.regalloc.RegisterAllocator;
import edu.kit.kastel.vads.compiler.ir.IrGraph;
import edu.kit.kastel.vads.compiler.ir.node.Node;
public class X86CodeGenerator implements CodeGenerator {
private static final String MAIN_ASM = """
.global main
.global _main
.text
main:
call _main
# move the return value into the first argument for the syscall
movq %rax, %rdi
# move the exit syscall number into rax
movq $0x3C, %rax
syscall
_main:
# your generated code here
""";
public String generateCode(List<IrGraph> program) {
StringBuilder builder = new StringBuilder();
for (IrGraph graph : program) {
RegisterAllocator allocator = new AasmRegisterAllocator();
Map<Node, Register> registers = allocator.allocateRegisters(graph);
builder.append(MAIN_ASM);
generateForGraph(graph, builder, registers);
}
return builder.toString();
}
private void generateForGraph(IrGraph graph, StringBuilder builder, Map<Node, Register> registers) {
Set<Node> visited = new HashSet<>();
scan(graph.endBlock(), visited, builder, registers);
}
private void scan(Node node, Set<Node> visited, StringBuilder builder, Map<Node, Register> registers) {
for (Node predecessor : node.predecessors()) {
if (visited.add(predecessor)) {
scan(predecessor, visited, builder, registers);
}
}
// TODO: implement code generation
switch (node) {
default:
throw new UnsupportedOperationException("Codegeneration for '" + node.toString() + "' is not implemented.");
}
}
}